//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
// M8051W/EW Verilog Definitions File
// 
// $Log: m8051w_defs.v,v $
// Revision 1.1  2001/11/20
// First checkin of version 2 features and name change
//
// Revision 1.1  2001/10/31
// First parsable verilog for EW
//
// Revision 1.1.1.1  2001/07/17
// Re-imported E-Warp from Farnham filesystem
//
// Revision 1.5  2000/10/24
// Multiplier rewritten to improve power consumption.
// Code changes for Leonardo (ECN01372).
// Code changes for formal verification tools (ECN01410).
// MOVX @Ri page address controllable from PORT2I if I/O ports ommitted (ECN01387).
//
// Revision 1.4  2000/03/17
// OCI update
//
// Revision 1.3  2000/02/05
// Name change repercussions
//
// Revision 1.2  2000/02/05
// Name change repercussions
//
// Revision 1.1  2000/02/05
// Renamed m8051ewarp as m8051ewarp
//
// Revision 1.2  1999/11/30
// More debug changes.
//
// Revision 1.1.1.1  1999/10/28
// "initialization and source check-in for m8051e"
//
// Revision 1.1  1999/10/22
// Initial revision
//
////////////////////////////////////////////////////////////////////////////////

// Enumeration of machine states

`define C1P1 (STATE == 3'b000)
`define C1P2 (STATE == 3'b001)
`define C2P1 (STATE == 3'b010)
`define C2P2 (STATE == 3'b011)
`define CLP1 (LAST_CYC && ~STATE[0])
`define CLP2 (LAST_CYC && STATE[0])

// Enumeration of SFR addresses

// Address definitions here are 7-bit.  The absolute address of an SFR is the
// value of the address space offset (80h) added to the address definition given
// below.

// Core SFRs
`define AddrSP    7'h01
`define AddrPCON  7'h07
`define AddrPSW   7'h50
`define AddrACC   7'h60
`define AddrB     7'h70

// Data Pointers
`define AddrDPL   7'h02
`define AddrDPH   7'h03
`define AddrDPL1  7'h04
`define AddrDPH1  7'h05
`define AddrEOR   7'h22		

// I/O ports
`define AddrP0    7'h00
`define AddrP1    7'h10
`define AddrP2    7'h20
`define AddrP3    7'h30

// Timer/Counters 0 and 1
`define AddrTCON  7'h08
`define AddrTMOD  7'h09
`define AddrTL0   7'h0A
`define AddrTL1   7'h0B
`define AddrTH0   7'h0C
`define AddrTH1   7'h0D

// Timer 2
`define AddrT2CON 7'h48
`define AddrRCP2L 7'h4A
`define AddrRCP2H 7'h4B
`define AddrTL2   7'h4C
`define AddrTH2   7'h4D

// Serial Interface
`define AddrSCON  7'h18
`define AddrSBUF  7'h19

// Interrupt Controller
`define AddrIE    7'h28
`define AddrIE1   7'h68
`define AddrIP    7'h38
`define AddrIP1   7'h78
`define AddrIPH   7'h39
`define AddrIP1H  7'h79

// memory paging Registers
`define AddrMEX1  7'h14
`define AddrMEX2  7'h15
`define AddrMEX3  7'h16
`define AddrMEXSP 7'h17
